On May 6th, at the TSMC North America Technology Symposium held last week, Tesla announced that its wafer-level Dojo processor for artificial intelligence training has entered mass production, bringing deployment closer.
It is reported that Tesla's Dojo system-on-wafer (SoW) processor (officially referred to as the Dojo Training Tile) employs a 5*5 array consisting of a total of 25 chips, each utilizing a 7nm process. These chips are placed on a carrier wafer and then interconnected using TSMC's Integrated Fan-Out (InFO) technology for wafer-level interconnects (InFO_SoW).
The InFO_SoW technology enables the 25 chips of Dojo to function as a single processor. To maintain consistency at the wafer level, TSMC fills the gaps between the chips with virtual chips.
By 2027, TSMC plans to integrate these wafer-level systems into wafers (SoIC) using advanced CoWoS packaging technology. By then, a complete wafer will provide 40 times the computing power, exceeding 40 mask layers of silicon, and up to 60 high-frequency wide memory chips.
Tesla's wafer-level Dojo processor actually contains 25 ultra-high-performance processors with very high power consumption, thus requiring complex cooling systems. To meet the power supply requirements of the Dojo processor, Tesla employs complex voltage regulation modules, providing 18,000 amps of power to the compute plane, dissipating up to 15,000W of heat, thus requiring water cooling for heat dissipation.
Tesla has not disclosed the performance of its Dojo wafer system, but considering all the challenges it has faced during development, it is expected to become a very powerful solution for artificial intelligence training.
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